In the computing industry it is quite common to transfer data and commands between a plurality of data processing devices, such as for example, computers, printers, memories and the like, across a system or data bus. The usual bus architecture includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed. For any bus connected to multiple agents (e.g., printed circuit boards) there arises a need for one agent (frequently referred to as the "source") to inform another agent (frequently referred to as the "destination") that it requires some sort of service. This mechanism by which a source informs a destination that it requires service is called a "request". The service requested can be in the form of data or other system information.
In a bus architecture where more than one agent can control the bus or gain ownership to inform the destination that it needs service, a mechanism must exist to decide which agent is permitted ownership of the bus at any particular time. Most often, a scheme known as "arbitration" is used. Arbitration allows the different agents to determine which agent will be the next bus owner. The decision as to who will be the next bus owner among the different agents is made on the basis of a priority which is reflected in the "arbitration number" used by the particular agent. That is, in an arbitration scheme, each agent is assigned a priority number which determines when that agent will become the next bus owner.
Various methods have been devised by particular bus architectures for sending interrupt requests or direct memory access (DMA) requests to the destination. Buses like Micro-channel, EISA, VME, and MultiBus I (e.g., "MBI") employ discrete interrupt or DMA request lines interconnected among the various agents. These discrete lines are not available in bus architectures like MultiBus II (e.g., "MBII").
In a bus architecture which employs discrete interrupt or DMA request lines, the source simply enables one of the discrete lines so that the destination is immediately notified that service has been requested. The destination agent can thereafter begin arbitrating for ownership of the bus. The latency, i.e., the time period between which the source enables one of the discrete interrupt or DMA request lines and the time that the destination responds, is dependent only upon the priority of the destination. As is appreciated by practitioners in the field, the chief drawback of the discrete interrupt or DMA lines request scheme is the obvious requirement of additional lines interconnected between the various agents. In a data processing system that includes many agents or boards, the number of required discrete interrupt or DMA lines can quickly become excessive.
As an alternative to separate sets of discrete interrupt request lines, other bus architectures have resorted to different methods. For example, in the MultiBus II architecture, the source sends an interrupt or DMA type of request to the destination in the form of a message. This approach is commonly referred to as a source request method. The message which is sent is simply a collection of data write cycles that contains appropriate information. This message, in the MBII case, is a block of 32 bytes containing an encoded request for interrupt or DMA service. The clear advantage of a bus architecture such as MultiBus II is that by eliminating the use of discrete request lines, many more potential sources are now available. Also, once bus ownership is granted to an agent, that agent can then send over the actual message.
In bus architectures which are similar to MBII, prior to sending a message to the destination the source must first arbitrate in order to become the bus owner. Once bus ownership has been granted, the source may then send the request message to the destination. The length of time between the source requesting service and the destination providing that service is called the latency period. Note that the latency can be very long since the source must first arbitrate for the bus using its own arbitration number. Next, it must send the interrupt request message to the destination after which time the destination can respond by arbitrating with its own arbitration number in order to service the source.
In other words, when servicing an interrupt or DMA request, the point at which the destination obtains service is based on the arbitration priority of both the agent requesting service (i.e., the source) and the agent providing service (i.e., the destination). If either the source or destination, or both, have a low priority in the arbitration scheme, (i.e., it is less likely to get control of the bus quickly) then the latency period can become very long.
Thus, there is a built-in time overhead for performing DMA or interrupt requests based on the need to arbitrate for control of the bus at both the source and destination points. The length of arbitration is dependant on the priority of both the source and the destination as reflected in their respective arbitration numbers. Accordingly, in data processing systems with multiple agents, a new interrupt or DMA request mechanism is needed which minimizes the latency period. Such a scheme would insure optimum efficiency in bus performance.
As will be described, the present invention provides a faster and simpler way by which a bus architecture such as MBII can support interrupt and DMA requests. According to the concept embodied by the present invention, the source uses the arbitration number of the destination--rather than its own arbitration number--when requesting service from the destination. This mechanism is called "destination request". In the destination request scheme of the present invention, the priority of the DMA or interrupt request is solely dependant on the arbitration number of the destination and not on the priority of the source. As a result, the latency period is reduced to levels comparable to that of bus architectures employing discrete interrupt or DMA request lines.